Complementary metal-oxide semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of static random access memory cells (SRAM). The reduction in size of SRAM cells has provided significant improvements in the speed, performance, circuit density, and cost per unit function of SRAM cells. However, as these memory cells are reduced in size, increases in the write margin, increases in the read margin, and reductions in the minimum operation voltage (Vcc,min) of the memory cell become more critical to its efficient operation.
FIG. 1 shows an eight-transistor (8T) SRAM memory cell 100. This 8T memory cell 100 has a first pass-gate transistor 101, a second pass-gate transistor 103, a third pass-gate transistor 115, a fourth pass-gate transistor 117, a first pull-up transistor 105, a second pull-up transistor 107, a first pull-down transistor 109, and a second pull-down transistor 111. In the 8T memory cell 100, the gates 113 of the pass-gate transistor 101 and the pass-gate transistor 115 are controlled by the first word line WL-1 and the gates 121 of the pass-gate transistor 103 and the pass-gate transistor 117 are controlled by the second word line WL-2 to determine whether the 8T memory cell 100 is selected or not selected. A latch formed of pull-up transistors 105 and 107 and pull-down transistors 109 and 111 stores a state. The stored state can be read through the bit line combination ABL/ABLB or the bit line combination BBL/BBLB.
In this configuration, the 8T memory cell 100 is written to by putting a low voltage on the first word line WL-1 while putting a high voltage on the second word line WL-2. Once a high voltage has been put onto the second word line WL-2, a high voltage is placed on the bit line BBL and complementary bit line BBLB, while keeping a low voltage on the bit line ABL and complementary bit line ABLB. To read from this memory device, a high voltage is put onto the first word line WL-1 and a low voltage is placed onto the second word line WL-2. Once a high voltage is placed onto the first word line WL-1, a high voltage is placed onto the bit line ABL and its complementary bit line ABLB while a low voltage is placed onto the bit line BBL and its complementary bit line BBLB.
FIG. 2 is an overlay view of the design of the 8T memory cell 100. This shows the inherent drawback to the 8T memory cell 100: its size. The 8T memory cell takes up considerably more space than a typical 6T memory cell. A typical 6T memory cell uses about 0.35 μm2 while the 8T memory cell 100 uses about 0.65 μm2.
What is needed, therefore, is a memory cell with eight transistors that has an improved read margin, an improved write margin, and a reduced Vcc,min, that also has a reduced area.